Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
Paul D. Gross, Ravishankar Arunachalam, Karthik Ra...
— The border gateway protocol (BGP) is known to take a long time to converge to a steady state following the failure of BGP routers or inter-router links. This has resulted in ex...
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
Distributed scheduling algorithms for wireless ad hoc networks have received substantial attention over the last decade. The complexity levels of these algorithms span a wide spec...
We use computer simulation to study the performance of alternative real-time delay estimators in heavily loaded multiserver queueing models. These delay estimates may be used to m...