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120
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ASAP
1996
IEEE
96views Hardware» more  ASAP 1996»
15 years 7 months ago
Kestrel: A Programmable Array for Sequence Analysis
Kestrel is a programmable linear array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, ...
Jeffrey D. Hirschberg, Richard Hughey, Kevin Karpl...
163
Voted
AI
1999
Springer
15 years 3 months ago
Cooperative Behavior Acquisition for Mobile Robots in Dynamically Changing Real Worlds Via Vision-Based Reinforcement Learning a
In this paper, we first discuss the meaning of physical embodiment and the complexity of the environment in the context of multi-agent learning. We then propose a vision-based rei...
Minoru Asada, Eiji Uchibe, Koh Hosoda
142
Voted
CODES
2007
IEEE
15 years 10 months ago
Improved response time analysis of tasks scheduled under preemptive Round-Robin
Round-Robin scheduling is the most popular time triggered scheduling policy, and has been widely used in communication networks for the last decades. It is an efficient schedulin...
Razvan Racu, Li Li, Rafik Henia, Arne Hamann, Rolf...
95
Voted
ICRA
2007
IEEE
127views Robotics» more  ICRA 2007»
15 years 10 months ago
A Comparative Dependability Analysis of Antagonistic Actuation Arrangements for Enhanced Robotic Safety
Abstract— In this paper we introduce an analysis of dependability of an elementary yet critical component of robotic systems designed to operate in environments shared with human...
Roberto Filippini, Soumen Sen, Giovanni Tonietti, ...
149
Voted
ICCD
2006
IEEE
118views Hardware» more  ICCD 2006»
16 years 19 days ago
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
Jinwen Xi, Peixin Zhong