Sciweavers

283 search results - page 15 / 57
» Effective Program Verification for Relaxed Memory Models
Sort
View
POPL
2009
ACM
16 years 9 days ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
106
Voted
DC
2010
14 years 11 months ago
Model checking transactional memories
Model checking software transactional memories (STMs) is difficult because of the unbounded number, length, and delay of concurrent transactions and the unbounded size of the memo...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
107
Voted
ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
14 years 11 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
107
Voted
ISCA
1992
IEEE
111views Hardware» more  ISCA 1992»
15 years 3 months ago
Lazy Release Consistency for Software Distributed Shared Memory
Relaxed memory consistency models, such as release consistency, were introduced in order to reduce the impact of remote memory access latency in both software and hardware distrib...
Peter J. Keleher, Alan L. Cox, Willy Zwaenepoel
TPHOL
2009
IEEE
15 years 6 months ago
A Better x86 Memory Model: x86-TSO
Abstract. Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory mode...
Scott Owens, Susmit Sarkar, Peter Sewell