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» Effective Program Verification for Relaxed Memory Models
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FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
15 years 6 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
ISPASS
2010
IEEE
15 years 4 months ago
Understanding transactional memory performance
Abstract—Transactional memory promises to generalize transactional programming to mainstream languages and data structures. The purported benefit of transactions is that they ar...
Donald E. Porter, Emmett Witchel
OOPSLA
2010
Springer
14 years 12 months ago
Efficient modular glass box software model checking
Glass box software model checking incorporates novel techniques to identify similarities in the state space of a model checker and safely prune large numbers of redundant states w...
Michael Roberson, Chandrasekhar Boyapati
IPCO
2004
110views Optimization» more  IPCO 2004»
15 years 3 months ago
Scheduling an Industrial Production Facility
Managing an industrial production facility requires carefully allocating limited resources, and gives rise to large, potentially complicated scheduling problems. In this paper we c...
Eyjolfur Asgeirsson, Jonathan W. Berry, Cynthia A....
ICASSP
2008
IEEE
15 years 8 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...