283 search results - page 38 / 57 » Effective Program Verification for Relaxed Memory Models |
PLDI
2011
ACM
14 years 2 months ago
2011
ACM
Exploiting today’s multiprocessors requires highperformance and correct concurrent systems code (optimising compilers, language runtimes, OS kernels, etc.), which in turn requir...
129
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TRIER
2002
14 years 11 months ago
2002
It is known that interprocedural detection of copy constants and elimination of faint code in parallel programs are undecidable problems, if base statements are assumed to execute...
CF
2009
ACM
15 years 6 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
103
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MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
105
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ARCS
2009
Springer
15 years 6 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...