Sciweavers

283 search results - page 45 / 57
» Effective Program Verification for Relaxed Memory Models
Sort
View
CODES
2006
IEEE
15 years 1 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
IPPS
2008
IEEE
15 years 6 months ago
A deterministic multi-way rendezvous library for haskell
The advent of multicore processors requires mainstream concurrent programming languages with high level concurrency constructs and effective debugging techniques. Unfortunately, m...
Nalini Vasudevan, Satnam Singh, Stephen A. Edwards
ICSE
2005
IEEE-ACM
15 years 11 months ago
Automatic discovery of API-level exploits
We argue that finding vulnerabilities in software components is different from finding exploits against them. Exploits that compromise security often use several low-level details...
Vinod Ganapathy, Sanjit A. Seshia, Somesh Jha, Tho...
74
Voted
SIGSOFT
2004
ACM
16 years 12 days ago
Heuristic-guided counterexample search in FLAVERS
One of the benefits of finite-state verification (FSV) tools, such as model checkers, is that a counterexample is provided when the property cannot be verified. Not all counterexa...
Jianbin Tan, George S. Avrunin, Lori A. Clarke, Sh...
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 4 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...