Sciweavers

345 search results - page 49 / 69
» Effective memory protection using dynamic tainting
Sort
View
ICS
1998
Tsinghua U.
15 years 1 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
195
Voted
POPL
2009
ACM
15 years 10 months ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
ISCA
2007
IEEE
177views Hardware» more  ISCA 2007»
15 years 4 months ago
Adaptive insertion policies for high performance caching
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applica...
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, ...
RAID
2007
Springer
15 years 3 months ago
SpyShield: Preserving Privacy from Spy Add-Ons
Spyware infections are becoming extremely pervasive, posing a grave threat to Internet users’ privacy. Control of such an epidemic is increasingly difficult for the existing def...
Zhuowei Li, XiaoFeng Wang, Jong Youl Choi
CORR
2010
Springer
164views Education» more  CORR 2010»
14 years 8 months ago
Securing AODV for MANETs using Message Digest with Secret Key
Due to lack of the infrastructure, open peer-to-peer architecture, shared wireless medium, limited resource constraints and highly dynamic topology, MANETs (Mobile Adhoc Networks) ...
Kamaljit I. Lakhtaria, Bhaskar N. Patel, Satish G....