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ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
15 years 5 months ago
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
QEST
2008
IEEE
15 years 6 months ago
Approximate Analysis of Probabilistic Processes: Logic, Simulation and Games
We tackle the problem of non robustness of simulation and bisimulation when dealing with probabilistic processes. It is important to ignore tiny deviations in probabilities becaus...
Josée Desharnais, François Laviolett...
DAM
2007
100views more  DAM 2007»
14 years 11 months ago
Memory management optimization problems for integrated circuit simulators
In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to ...
Timothée Bossart, Alix Munier Kordon, Franc...
PADS
2004
ACM
15 years 5 months ago
Exploiting Symmetry for Partitioning Models in Parallel Discrete Event Simulation
We investigated the benefit of exploiting the symmetries of graphs for partitioning. We represent the model to be simulated by a weighted graph. Graph symmetries are studied in th...
Jan Lemeire, Bart Smets, Philippe Cara, Erik F. Di...
CSL
2006
Springer
15 years 3 months ago
Visibly Pushdown Automata: From Language Equivalence to Simulation and Bisimulation
Abstract. We investigate the possibility of (bi)simulation-like preorder/equivalence checking on the class of visibly pushdown automata and its natural subclasses visibly BPA (Basi...
Jirí Srba