61 search results - page 5 / 13 » Effectively sharing a cache among threads |
CGO
2004
IEEE
15 years 1 months ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...
JSSPP
2010
Springer
14 years 7 months ago
2010
Springer
This paper proposes and evaluates APIs for Inter-Core Time Aggregation Scheduler (IAS), which is a kernel-level thread scheduler to enhance performances of multi-threaded programs ...
74
Voted
DAMON
2007
Springer
15 years 3 months ago
2007
Springer
Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among ...
72
Voted
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...