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RTSS
1996
IEEE
15 years 2 months ago
Reducing the number of clock variables of timed automata
We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks wh...
Conrado Daws, Sergio Yovine
ISPD
2009
ACM
79views Hardware» more  ISPD 2009»
15 years 4 months ago
A routing approach to reduce glitches in low power FPGAs
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
Quang Dinh, Deming Chen, Martin D. F. Wong
PR
2008
129views more  PR 2008»
14 years 10 months ago
A comparison of generalized linear discriminant analysis algorithms
7 Linear discriminant analysis (LDA) is a dimension reduction method which finds an optimal linear transformation that maximizes the class separability. However, in undersampled p...
Cheong Hee Park, Haesun Park
PKC
2009
Springer
121views Cryptology» more  PKC 2009»
15 years 10 months ago
Fast Multibase Methods and Other Several Optimizations for Elliptic Curve Scalar Multiplication
Recently, the new Multibase Non-Adjacent Form (mbNAF) method was introduced and shown to speed up the execution of the scalar multiplication with an efficient use of multiple bases...
Patrick Longa, Catherine H. Gebotys
TCAD
2008
136views more  TCAD 2008»
14 years 10 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar