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77
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DAC
2008
ACM
14 years 11 months ago
2008
ACM
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
107
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LCTRTS
2005
Springer
15 years 3 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
SC
2009
ACM
15 years 4 months ago
2009
ACM
In this paper, we present an early performance evaluation of a 624-core cluster based on the Intel® Xeon® Processor 5560 (code named “Nehalem-EP”, and referred to as Xeon 55...
CORR
2011
Springer
14 years 4 months ago
2011
Springer
We provide an overall description of the Ciao multiparadigm programming system emphasizing some of the novel aspects and motivations behind its design and implementation. An impor...