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DATE
2010
IEEE
139views Hardware» more  DATE 2010»
15 years 5 months ago
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocate...
Jun Zhu, Ingo Sander, Axel Jantsch
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
15 years 7 months ago
Efficient link capacity and QoS design for network-on-chip
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israe...
IPPS
2005
IEEE
15 years 7 months ago
Using Leader-Based Communication to Improve the Scalability of Single-Round Group Membership Algorithms
Sigma, the first single-round group membership (GM) algorithm, was recently introduced and demonstrated to operate consistently with theoretical expectations in a simulated WAN en...
Roger Khazan, Sophia Yuditskaya
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
15 years 5 months ago
Context-Aware Performance Analysis for Efficient Embedded System Design
Performance analysis has many advantages in theory compared to simulation for the validation of complex embedded systems, but is rarely used in practice. To make analysis more att...
Marek Jersak, Rafik Henia, Rolf Ernst
ICA3PP
2005
Springer
15 years 7 months ago
A Low-Level Communication Library for Java HPC
Abstract. Designing a simple but powerful low-level communication library for Java HPC environments is an important task. We introduce new low-level communication library for Java ...
Sang Boem Lim, Bryan Carpenter, Geoffrey Fox, Han-...