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ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
RSP
2005
IEEE
131views Control Systems» more  RSP 2005»
15 years 3 months ago
Models for Embedded Application Mapping onto NoCs: Timing Analysis
Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of N...
César A. M. Marcon, Márcio Eduardo K...
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
15 years 2 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
APPROX
2008
Springer
184views Algorithms» more  APPROX 2008»
14 years 11 months ago
Approximately Counting Embeddings into Random Graphs
Let H be a graph, and let CH(G) be the number of (subgraph isomorphic) copies of H contained in a graph G. We investigate the fundamental problem of estimating CH(G). Previous res...
Martin Fürer, Shiva Prasad Kasiviswanathan
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
14 years 11 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang