Sciweavers

95 search results - page 4 / 19
» Efficient Design and Analysis of Robust Power Distribution M...
Sort
View
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 9 days ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
13 years 11 months ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
14 years 3 months ago
Robust analog/RF circuit design with projection-based posynomial modeling
In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthe...
Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence ...
TASE
2011
IEEE
12 years 10 months ago
Fast Intersection-Free Offset Surface Generation From Freeform Models With Triangular Meshes
Abstract—A fast offset surface generation approach is presented in this paper to construct intersection-free offset surfaces, which preserve sharp features, from freeform triangu...
Shengjun Liu, Charlie C. L. Wang