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HIPC
2005
Springer
15 years 3 months ago
Preemption Adaptivity in Time-Published Queue-Based Spin Locks
Abstract. The proliferation of multiprocessor servers and multithreaded applications has increased the demand for high-performance synchronization. Traditional scheduler-based lock...
Bijun He, William N. Scherer III, Michael L. Scott
CODES
2010
IEEE
14 years 7 months ago
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
Daniel Cordes, Peter Marwedel, Arindam Mallik
83
Voted
FCCM
2009
IEEE
189views VLSI» more  FCCM 2009»
15 years 4 months ago
Application Specific Customization and Scalability of Soft Multiprocessors
Although soft microprocessors are widely used in FPGAs, limited work has been performed regarding how to automatically and efficiently generate soft multiprocessors. In this paper...
Deepak Unnikrishnan, Jia Zhao, Russell Tessier
DSD
2006
IEEE
83views Hardware» more  DSD 2006»
15 years 1 months ago
Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication
Abstract. Network-on-chip-based multiprocessor systems-onchip are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel p...
Sander Stuijk, Twan Basten, Marc Geilen, Amir Hoss...
WSC
1997
14 years 11 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson