53 search results - page 5 / 11 » Efficient Interconnects for Clustered Microarchitectures |
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
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HPCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Parallel computing on clusters of workstations is attractive because of the low costs in comparison to MPPs, but the speed of the local area network limits the class of applicatio...
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
MICRO
1999
IEEE
15 years 1 months ago
1999
IEEE
The speculative multithreading paradigm (speculative threadlevel parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitect...
FPL
2008
Springer
14 years 11 months ago
2008
Springer
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...