Sciweavers

279 search results - page 8 / 56
» Efficient Power Co-Estimation Techniques for System-on-Chip ...
Sort
View
VLSISP
2008
147views more  VLSISP 2008»
14 years 10 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
TVLSI
2002
97views more  TVLSI 2002»
14 years 11 months ago
Techniques for energy-efficient communication pipeline design
The performance of many modern computer and communication systems is dictated by the latency of communication pipelines. At the same time, power/energy consumption is often another...
Gang Qu, Miodrag Potkonjak
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
16 years 4 days ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
15 years 5 months ago
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique
In this paper, we present a novel multigrid-based technique for power/ground mesh area optimization subject to reliability constraints. The multigrid-based technique is applied to...
Kai Wang, Malgorzata Marek-Sadowska
VLSID
2007
IEEE
128views VLSI» more  VLSID 2007»
16 years 4 days ago
A Low Power Frequency Multiplication Technique for ZigBee Transciever
A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a g...
Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj...