Sciweavers

61 search results - page 10 / 13
» Efficient Run-Time Monitoring of Timing Constraints
Sort
View
91
Voted
INFOCOM
2010
IEEE
14 years 7 months ago
MeasuRouting: A Framework for Routing Assisted Traffic Monitoring
Monitoring transit traffic at one or more points in a network is of interest to network operators for reasons of traffic accounting, debugging or troubleshooting, forensics, and tr...
Saqib Raza, Guanyao Huang, Chen-Nee Chuah, Srini S...
DEBS
2009
ACM
15 years 1 months ago
Efficient event-based resource discovery
The ability to find services or resources that satisfy some criteria is an important aspect of distributed systems. This paper presents an event-based architecture to support more...
Wei Yan, Songlin Hu, Vinod Muthusamy, Hans-Arno Ja...
INTEGRATION
2008
127views more  INTEGRATION 2008»
14 years 8 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...

Publication
198views
15 years 22 days ago
Real time policy based management of workflows for SLA Adherence
The need for service providers to offer SLAs to gain consumers confidence has become increasingly apparent. Our work focuses on providers who manage the execution of long-running d...
Daniel Spaven, Madhavi Rani, Sumit Kumar Bose, Mik...
70
Voted
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 3 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...