7 search results - page 1 / 2 » Efficient Runahead Execution: Power-Efficient Memory Latency... |
71
Voted
MICRO
2006
IEEE
14 years 9 months ago
2006
IEEE
Runahead execution improves memory latency tolerance without significantly increasing processor complexity. Unfortunately, a runahead execution processor executes significantly mo...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
HPCA
1999
IEEE
15 years 1 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
102
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ICPP
1999
IEEE
15 years 1 months ago
1999
IEEE
The probability of failures in software distributed shared memory (SDSM) increases as the system size grows. This paper introduces a new, efficient message logging technique, call...