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ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
15 years 3 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
FPL
2000
Springer
119views Hardware» more  FPL 2000»
15 years 1 months ago
A Self-Reconfigurable Gate Array Architecture
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro M...
TVLSI
2008
164views more  TVLSI 2008»
14 years 9 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
ERSA
2010
172views Hardware» more  ERSA 2010»
14 years 7 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
76
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RECOSOC
2007
118views Hardware» more  RECOSOC 2007»
14 years 11 months ago
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems
Electronic equipments with higher performance, lower power consumption, and smaller size motivate the research for more efficient design methods. Platform-based design is a method...
Leandro Möller, Ismael Grehs, Ewerson Carvalh...