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CODES
2005
IEEE
13 years 12 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
GRID
2007
Springer
14 years 12 days ago
Load prediction using hybrid model for computational grid
—Due to the dynamic nature of grid environments, schedule algorithms always need assistance of a long-time-ahead load prediction to make decisions on how to use grid resources ef...
Yongwei Wu, Yulai Yuan, Guangwen Yang, Weimin Zhen...
CVPR
2004
IEEE
14 years 8 months ago
Propagation Networks for Recognition of Partially Ordered Sequential Action
We present Propagation Networks (P-Nets), a novel approach for representing and recognizing sequential activities that include parallel streams of action. We represent each activi...
Yifan Shi, Yan Huang, David Minnen, Aaron F. Bobic...
ICIP
2010
IEEE
13 years 4 months ago
Dual Range Deringing for non-blind image deconvolution
The popular Richardson-Lucy (RL) image deconvolution algorithm often produces undesirable ringing artifacts. In this paper, we propose a novel Dual Range Deringing (DRD) algorithm...
Le Zou, Howard Zhou, Samuel Cheng, Chuan He
HPCA
2007
IEEE
14 years 6 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou