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DAC
2005
ACM
16 years 26 days ago
2005
ACM
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
DAC
2005
ACM
16 years 26 days ago
2005
ACM
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
117
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GLVLSI
2010
IEEE
15 years 1 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
130
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TVLSI
2008
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
14 years 11 months ago
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
FLAIRS
2004
15 years 1 months ago
2004
It is a vital and challenging issue in AI community to get the "Right Information" to the "Right People" in the "Right Language" in the "Right T...