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DAC
2003
ACM
16 years 26 days ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 4 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
DATE
2009
IEEE
143views Hardware» more  DATE 2009»
15 years 6 months ago
Dimensioning heterogeneous MPSoCs via parallelism analysis
—In embedded computing we face a continuously growing algorithm complexity combined with a constantly rising number of applications running on a single system. Multi-core systems...
Bastian Ristau, Torsten Limberg, Oliver Arnold, Ge...
DAC
2006
ACM
16 years 26 days ago
Predicate learning and selective theory deduction for a difference logic solver
Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
Chao Wang, Aarti Gupta, Malay K. Ganai
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
15 years 4 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...