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DATE
2004
IEEE
110views Hardware» more  DATE 2004»
15 years 1 months ago
Interactive Cosimulation with Partial Evaluation
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimizatio...
Patrick Schaumont, Ingrid Verbauwhede
USENIX
1990
14 years 10 months ago
Efficient User-Level File Cache Management on the Sun Vnode Interface
In developing a distributed file system, there are several good reasons for implementing the client file cache manager as a user-level process. These include ease of implementatio...
David C. Steere, James J. Kistler, Mahadev Satyana...
DAC
1999
ACM
15 years 10 months ago
Power Efficient Mediaprocessors: Design Space Exploration
We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a catego...
Johnson Kin, Chunho Lee, William H. Mangione-Smith...
ICSE
2004
IEEE-ACM
15 years 9 months ago
Assume-Guarantee Verification of Source Code with Design-Level Assumptions
Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. To address the "state explosion" problem a...
Dimitra Giannakopoulou, Corina S. Pasareanu, Jamie...
ICCAD
2009
IEEE
133views Hardware» more  ICCAD 2009»
14 years 7 months ago
A parallel preconditioning strategy for efficient transistor-level circuit simulation
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...
Heidi Thornquist, Eric R. Keiter, Robert J. Hoekst...