We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iri...
This paper extends our earlier results. We assume that the receiver has the capability of capturing multiple packets so long as the signal-to-interference-plus-noise ratio (SINR) o...
Performance analysis has many advantages in theory compared to simulation for the validation of complex embedded systems, but is rarely used in practice. To make analysis more att...
This research examines the performance of CONWIP versus "push" workload control in a simple, balanced manufacturing flowline. Analytical models and simulation experiment...
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...