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WSC
1997
15 years 1 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
15 years 5 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
15 years 8 months ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...
SCFBM
2008
112views more  SCFBM 2008»
14 years 11 months ago
The Multiscale Systems Immunology project: software for cell-based immunological simulation
Background: Computer simulations are of increasing importance in modeling biological phenomena. Their purpose is to predict behavior and guide future experiments. The aim of this ...
Faheem Mitha, Timothy A. Lucas, Feng Feng, Thomas ...
DAC
2007
ACM
16 years 24 days ago
Shared Resource Access Attributes for High-Level Contention Models
Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of indiv...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas