1466 search results - page 51 / 294 » Efficient Simulation of Synthesis-Oriented System Level Desi... |
IWSOC
2003
IEEE
15 years 5 months ago
2003
IEEE
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
VLSID
2003
IEEE
16 years 6 days ago
2003
IEEE
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
SIGCSE
2009
ACM
16 years 12 days ago
2009
ACM
ion and Extensibility in Digital Logic Simulation Software Richard M. Salter and John L. Donaldson Computer Science Department Oberlin College Oberlin, OH 44074 rms@cs.oberlin.edu,...
105
click to vote
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
134
click to vote
IAJIT
2010
14 years 9 months ago
2010
: Finite Radon Transform mapper has the ability to increase orthogonality of sub-carriers, it is non sensitive to channel parameters variations, and has a small constellation energ...