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86
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ITC
2003
IEEE
222views Hardware» more  ITC 2003»
15 years 2 months ago
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
Mahesh A. Iyer
84
Voted
ISSS
2002
IEEE
144views Hardware» more  ISSS 2002»
15 years 2 months ago
A Visual Approach to Validating System Level Designs
This paper proposes a simulation-based methodology for validation of a system under design in an early phase of development. The key element of this approach is the visual speciļ¬...
Jürgen Ruf, Thomas Kropf, Jochen Klose
ICC
2009
IEEE
152views Communications» more  ICC 2009»
14 years 7 months ago
System Spectral Efficiency and Stability of 3G Networks: A Comparative Study
CDMA2000, WCDMA and WiMAX are three widely used 3G technologies. Since they share the same goal, which is to provide broader coverage and higher throughput in 3G networks, an impar...
Yuehong Gao, Xin Zhang, Yuming Jiang, Jeong-woo Ch...
90
Voted
ISSS
2002
IEEE
124views Hardware» more  ISSS 2002»
15 years 2 months ago
A New Performance Evaluation Approach for System Level Design Space Exploration
Application specific systems have potential for customization of design with a view to achieve a better costperformance-power trade-off. Such customization requires extensive de...
M. Balakrishnan, Anshul Kumar, C. P. Joshi
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
15 years 2 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann