19 search results - page 3 / 4 » Efficient Sorting Using Registers and Caches |
DCC
2008
IEEE
14 years 12 months ago
2008
IEEE
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
108
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HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
118
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TVLSI
2010
14 years 4 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
SPAA
2010
ACM
14 years 10 months ago
2010
ACM
Given the sequential implementation of any data structure, we show how to obtain an efficient, wait-free implementation of that data structure shared by any fixed number of proces...
132
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CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...