245 search results - page 6 / 49 » Efficient Symbolic Model Checking for Process Algebras |
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
FM
2003
Springer
15 years 2 months ago
2003
Springer
Counterexamples explain why a desired temporal logic property fails to hold, and as such are considered to be the most useful form of output from model-checkers. Multi-valued model...
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GLVLSI
2000
IEEE
15 years 1 months ago
2000
IEEE
Symbolic Model checking is a widely used technique in sequential verification. As the size of the OBDDs and also the computation time depends on the order of the input variables,...
TASE
2008
IEEE
15 years 3 months ago
2008
IEEE
Verification techniques like SAT-based bounded model checking have been successfully applied to a variety of system models. Applying bounded model checking to compositional proce...
FMCAD
2004
Springer
15 years 2 months ago
2004
Springer
We consider the problem of checking whether an incomplete design can still be extended to a complete design satisfying a given CTL formula and whether the property is satisfied fo...