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ATS
2009
IEEE
99views Hardware» more  ATS 2009»
15 years 4 months ago
Test Generation for Designs with On-Chip Clock Generators
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Xijiang Lin, Mark Kassab
IEEEPACT
2003
IEEE
15 years 3 months ago
Design Trade-Offs in High-Throughput Coherence Controllers
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
Anthony-Trung Nguyen, Josep Torrellas
VLSID
1999
IEEE
97views VLSI» more  VLSID 1999»
15 years 2 months ago
A New Methodology for Concurrent Technology Development and Cell Library Optimization
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, P...
GPC
2008
Springer
14 years 10 months ago
An Automatic and Scalable Testing Tool for Workflow Systems
Nowadays workflow systems are widely deployed around the world, especially within large international corporations. Thus the performance evaluation of these workflow systems becom...
Lin Quan, Xiaozhu Lin, Jianmin Wang
MASCOTS
2010
14 years 11 months ago
PAC: Pattern-driven Application Consolidation for Efficient Cloud Computing
To reduce cloud system resource cost, application consolidation is a must. In this paper, we present a novel patterndriven application consolidation (PAC) system to achieve efficie...
Zhenhuan Gong, Xiaohui Gu