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» Efficient Tree Layout in a Multilevel Memory Hierarchy
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IFL
2000
Springer
15 years 1 months ago
Improving Cache Effectiveness through Array Data Layout Manipulation in SAC
Sac is a functional array processing language particularly designed with numerical applications in mind. In this field the runtime performance of programs critically depends on the...
Clemens Grelck
DAC
2001
ACM
15 years 10 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
PODS
2006
ACM
216views Database» more  PODS 2006»
15 years 10 months ago
Cache-oblivious string B-trees
B-trees are the data structure of choice for maintaining searchable data on disk. However, B-trees perform suboptimally ? when keys are long or of variable length, ? when keys are...
Michael A. Bender, Martin Farach-Colton, Bradley C...
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
15 years 10 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
EUROPAR
2006
Springer
15 years 1 months ago
Optimization of Dense Matrix Multiplication on IBM Cyclops-64: Challenges and Experiences
Abstract. This paper presents a study of performance optimization of dense matrix multiplication on IBM Cyclops-64(C64) chip architecture. Although much has been published on how t...
Ziang Hu, Juan del Cuvillo, Weirong Zhu, Guang R. ...