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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
15 years 3 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
RTCSA
2005
IEEE
15 years 3 months ago
RTPS Middleware for Real-Time Distributed Industrial Vision Systems
Designing and constructing Real-Time Distributed Industrial Vision Systems (RT-DIVS) from scratch is very complicated task. RT-DIVS has Conflicting requirements such as reasonable...
Basem Almadani
VL
2005
IEEE
15 years 3 months ago
Transformation of UML State Machines for Direct Execution
Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In ...
Tim Schattkowsky, Wolfgang Müller 0003
WCRE
2005
IEEE
15 years 3 months ago
Enhancing Security Using Legality Assertions
Buffer overflows have been the most common form of security vulnerability in the past decade. A number of techniques have been proposed to address such attacks. Some are limited t...
Lei Wang, James R. Cordy, Thomas R. Dean
WSE
2005
IEEE
15 years 3 months ago
A Comprehensive Model for Web Sites Quality
Many of existing criteria for evaluating web sites quality require methods such as heuristic evaluations, or/and empirical usability tests. This paper aims at defining a quality m...
Oreste Signore