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CODES
2003
IEEE
15 years 3 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
CODES
2000
IEEE
15 years 2 months ago
Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off
This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance require...
Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Stee...
ICS
1994
Tsinghua U.
15 years 1 months ago
Evaluating automatic parallelization for efficient execution on shared-memory multiprocessors
We present a parallel code generation algorithm for complete applications and a new experimental methodology that tests the efficacy of our approach. The algorithm optimizes for d...
Kathryn S. McKinley
CODES
2006
IEEE
14 years 11 months ago
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buff...
Maarten Wiggers, Marco Bekooij, Pierre G. Jansen, ...
TACAS
2010
Springer
160views Algorithms» more  TACAS 2010»
14 years 7 months ago
Efficient Detection of Errors in Java Components Using Random Environment and Restarts
Software model checkers are being used mostly to discover specific types of errors in the code, since exhaustive verification of complex programs is not possible due to state explo...
Pavel Parizek, Tomás Kalibera