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» Efficient Wire Formats for High Performance Computing
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ISPAN
2000
IEEE
15 years 4 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras
SIPS
2007
IEEE
15 years 6 months ago
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (...
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu
IPPS
1998
IEEE
15 years 4 months ago
High Performance Data Mining Using Data Cubes on Parallel Computers
On-Line Analytical Processing techniques are used for data analysis and decision support systems. The multidimensionality of the underlying data is well represented by multidimens...
Sanjay Goil, Alok N. Choudhary
APCSAC
2001
IEEE
15 years 3 months ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
TCAD
2008
106views more  TCAD 2008»
14 years 11 months ago
Track Routing and Optimization for Yield
Abstract--In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probabi...
Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan