1259 search results - page 12 / 252 » Efficient Wire Formats for High Performance Computing |
137
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HPCA
2003
IEEE
16 years 2 days ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
113
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ICS
2009
Tsinghua U.
14 years 9 months ago
2009
Tsinghua U.
This paper presents high-performance collective communication algorithms and implementations that exploit the unique architectural features of the Cell heterogeneous multicore pro...
VLSID
2005
IEEE
16 years 3 days ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
120
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GLOBECOM
2008
IEEE
14 years 12 months ago
2008
IEEE
Hash functions have a space complexity of O(n) and a possible time complexity of O(1). Thus, packet classifiers exploit hashing to achieve packet classification in wire speed. Esp...
126
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SP
2002
IEEE
14 years 11 months ago
2002
IEEE
When Java was first introduced, there was a perception that its many benefits came at a significant performance cost. In the particularly performance-sensitive field of numerical ...