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ICS
2009
Tsinghua U.
15 years 11 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...
ESTIMEDIA
2009
Springer
15 years 2 months ago
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, ...
WWW
2008
ACM
16 years 5 months ago
Using graphics processors for high-performance IR query processing
Web search engines are facing formidable performance challenges due to data sizes and query loads. The major engines have to process tens of thousands of queries per second over t...
Shuai Ding, Jinru He, Hao Yan, Torsten Suel
ASPLOS
2009
ACM
16 years 5 months ago
QR decomposition on GPUs
QR decomposition is a computationally intensive linear algebra operation that factors a matrix A into the product of a unitary matrix Q and upper triangular matrix R. Adaptive sys...
Andrew Kerr, Dan Campbell, Mark Richards

Publication
314views
17 years 2 months ago
LED: Load Early Detection: A Congestion Control Algorithm based on Router Traffic Load
Efficient bandwidth allocation and low delays remain important goals, expecially in high-speed networks. Existing end-to-end congestion control schemes (such as TCP+AQM/RED) have s...
A. Durresi, P. Kandikuppa, M. Sridharan, S. Chella...