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» Efficient Wire Formats for High Performance Computing
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ICPP
2005
IEEE
15 years 10 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
FCCM
2006
IEEE
111views VLSI» more  FCCM 2006»
15 years 10 months ago
Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components
FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing r...
Robert Strzodka, Dominik Göddeke
135
Voted
IEEEPACT
2005
IEEE
15 years 10 months ago
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
Ben Wun, Jeremy Buhler, Patrick Crowley
EUROPAR
2006
Springer
15 years 8 months ago
An Embedded Systems Programming Environment for C
Resource constraints are a major concern with the design, development, and deployment of embedded systems. Embedded systems are highly hardware-dependent and have little computatio...
Bernd Burgstaller, Bernhard Scholz, M. Anton Ertl
CGF
2008
200views more  CGF 2008»
15 years 4 months ago
Deep Opacity Maps
We present a new method for rapidly computing shadows from semi-transparent objects like hair. Our deep opacity maps method extends the concept of opacity shadow maps by using a d...
Cem Yuksel, John Keyser