1259 search results - page 16 / 252 » Efficient Wire Formats for High Performance Computing |
132
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SIGGRAPH
1994
ACM
15 years 6 months ago
1994
ACM
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
121
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MOBISYS
2006
ACM
16 years 1 months ago
2006
ACM
The majority of security schemes available for sensor networks assume deployment in areas without access to a wired infrastructure. More specifically, nodes in these networks are ...
101
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WCE
2007
15 years 3 months ago
2007
—The JPEG 2000 image coding standard employs the biorthogonal 9/7 wavelet for lossy compression. The performance of hardware implementation of 9/7-filter bank depends on accuracy...
105
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VLSID
2006
IEEE
16 years 2 months ago
2006
IEEE
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round...
CORR
2008
Springer
15 years 2 months ago
2008
Springer
This paper presents the architecture and characteristics of a memory database intended to be used as a cache engine for web applications. Primary goals of this database are speed a...