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» Efficient Wire Formats for High Performance Computing
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CVPR
2010
IEEE
16 years 9 days ago
Automatic Discovery of Meaningful Object Parts with Latent CRFs
Object recognition is challenging due to high intra-class variability caused, e.g., by articulation, viewpoint changes, and partial occlusion. Successful methods need to strike a...
Paul Schnitzspan, Stefan Roth, Bernt Schiele
NOCS
2009
IEEE
15 years 10 months ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...
ICCS
2005
Springer
15 years 9 months ago
SWAT: A New Spliced Alignment Tool Tailored for Handling More Sequencing Errors
Abstract. There are several computer programs that align mRNA with its genomic counterpart to determine exon boundaries. Though most of these programs perform such alignment effici...
Yifeng Li, Hesham H. Ali
DAC
2003
ACM
15 years 9 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
ICPP
1998
IEEE
15 years 8 months ago
Supporting Software Distributed Shared Memory with an Optimizing Compiler
To execute a shared memory program efficiently, we have to manage memory consistency with low overheads, and have to utilize communication bandwidth of the platform as much as pos...
Tatsushi Inagaki, Junpei Niwa, Takashi Matsumoto, ...