1259 search results - page 44 / 252 » Efficient Wire Formats for High Performance Computing |
111
click to vote
SLIP
2003
ACM
15 years 9 months ago
2003
ACM
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
143
click to vote
ICIP
2009
IEEE
15 years 1 months ago
2009
IEEE
Kernel-based methods, e.g., support vector machine (SVM), produce high classification performances. However, the computation becomes time-consuming as the number of the vectors su...
136
click to vote
AINA
2008
IEEE
15 years 10 months ago
2008
IEEE
Wireless Sensor Networks (WSN) have specific constraints and stringent requirements in contrast to traditional wired and wireless computer networks. Among these specific requireme...
123
click to vote
IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
Dynamically allocating computing nodes to parallel applications is a promising technique for improving the utilization of cluster resources. We introduce the concept of dynamic ef...
149
click to vote
TCAD
2002
15 years 3 months ago
2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...