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» Efficient Wire Formats for High Performance Computing
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ISCAPDCS
2007
15 years 5 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
HPCA
2009
IEEE
16 years 4 months ago
A low-radix and low-diameter 3D interconnection network design
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
Bo Zhao, Jun Yang 0002, Xiuyi Zhou, Yi Xu, Youtao ...
ICPP
2007
IEEE
15 years 10 months ago
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
AI
2000
Springer
15 years 4 months ago
Wrapper induction: Efficiency and expressiveness
The Internet presents numerous sources of useful information--telephone directories, product catalogs, stock quotes, event listings, etc. Recently, many systems have been built th...
Nicholas Kushmerick
REFSQ
2009
Springer
15 years 11 months ago
A Controlled Experiment of a Method for Early Requirements Triage Utilizing Product Strategies
[Context and motivation] In market-driven product development of software intensive products large numbers of requirements threaten to overload the development organization. It is ...
Mahvish Khurum, Tony Gorschek, Lefteris Angelis, R...