1259 search results - page 97 / 252 » Efficient Wire Formats for High Performance Computing |
121
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GLVLSI
2009
IEEE
15 years 11 months ago
2009
IEEE
This paper proposes a scheme for automatic re-distribution layer (RDL) routing, which is used in chip-package connections. Traditional RDL routing designs are mostly performed man...
161
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ERSA
2006
15 years 5 months ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
160
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TIP
2010
14 years 11 months ago
2010
In this paper, we present a distributed multicamera face tracking system suitable for large wired camera networks. Unlike previous multicamera face tracking systems, our system doe...
128
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ISCA
2000
IEEE
15 years 8 months ago
2000
IEEE
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and lo...
217
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SIGMOD
2009
ACM
16 years 4 months ago
2009
ACM
In the rank join problem we are given a relational join R1 1 R2 and a function that assigns numeric scores to the join tuples, and the goal is to return the tuples with the highes...