171 search results - page 1 / 35 » Efficient algorithms for interface timing verification |
EURODAC
1994
IEEE
15 years 5 months ago
1994
IEEE
92
Voted
ISCAS
1999
IEEE
15 years 5 months ago
1999
IEEE
In this paper, we present a new method for verifying the realizability of a timing diagram with linear timing constraints, thus ensuring that the implementation of the underlying ...
87
Voted
DAC
2010
ACM
15 years 5 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
94
Voted
ICALP
2000
Springer
15 years 4 months ago
2000
Springer
We study the problem of strong/weak bisimilarity between processes of one-counter automata and finite-state processes. We show that the problem of weak bisimilarity between process...
98
Voted
ICCAD
2003
IEEE
15 years 10 months ago
2003
IEEE
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...