171 search results - page 4 / 35 » Efficient algorithms for interface timing verification |
108
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ASPDAC
1998
ACM
15 years 5 months ago
1998
ACM
Binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. Efficient BDD construction techniques become more important as the complexity of proto...
151
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CHARME
2003
Springer
15 years 5 months ago
2003
Springer
Abstract. We propose new, tractably (in some cases provably) efficient algorithmic methods for exact (sound and complete) parameterized reasoning about cache coherence protocols. F...
113
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DAC
2009
ACM
16 years 2 months ago
2009
ACM
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
FMCAD
2000
Springer
15 years 5 months ago
2000
Springer
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
115
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RTSS
1996
IEEE
15 years 6 months ago
1996
IEEE
We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks wh...