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ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
15 years 2 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler
ENTCS
2008
94views more  ENTCS 2008»
14 years 9 months ago
A Formal Model of Memory Peculiarities for the Verification of Low-Level Operating-System Code
This paper presents our solutions to some problems we encountered in an ongoing attempt to verify the micro-hypervisor currently developed within the Robin project. The problems t...
Hendrik Tews, Tjark Weber, Marcus Völp
FCSC
2008
87views more  FCSC 2008»
14 years 9 months ago
On the verification of polynomial system solvers
Abstract. We discuss the verification of mathematical software solving polynomial systems symbolically by way of triangular decomposition. Standard verification techniques are high...
Changbo Chen, Marc Moreno Maza, Wei Pan, Yuzhen Xi...
IFM
2010
Springer
205views Formal Methods» more  IFM 2010»
14 years 7 months ago
Adding Change Impact Analysis to the Formal Verification of C Programs
Handling changes to programs and specifications efficiently is a particular challenge in formal software verification. Change impact analysis is an approach to this challenge where...
Serge Autexier, Christoph Lüth
BMCBI
2010
128views more  BMCBI 2010»
14 years 9 months ago
VIGOR, an annotation program for small viral genomes
Background: The decrease in cost for sequencing and improvement in technologies has made it easier and more common for the re-sequencing of large genomes as well as parallel seque...
Shiliang Wang, Jaideep P. Sundaram, David Spiro