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» Efficient and User-Friendly Verification
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CHARME
2003
Springer
73views Hardware» more  CHARME 2003»
15 years 1 months ago
Towards Diagrammability and Efficiency in Event Sequence Languages
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...
Kathi Fisler
SP
2000
IEEE
15 years 2 months ago
An Efficient, Dynamic and Trust Preserving Public Key Infrastructure
Nested certification is a methodology for efficient certificate path verification. Nested certificates can be used together with classical certificates in the Public Key Infrastru...
Albert Levi, M. Ufuk Çaglayan
DAC
2009
ACM
15 years 10 months ago
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
Himanshu Jain, Edmund M. Clarke
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
15 years 4 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
ENTCS
2002
80views more  ENTCS 2002»
14 years 9 months ago
Monotonic Extensions of Petri Nets: Forward and Backward Search Revisited
In this paper, we revisit the forward and backward approaches to the verification of extensions of infinite state Petri Nets. As contributions, we propose an efficient data struct...
Alain Finkel, Jean-François Raskin, Mathias...