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» Efficient and User-Friendly Verification
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DATE
2006
IEEE
117views Hardware» more  DATE 2006»
15 years 3 months ago
Formal verification of systemc designs using a petri-net based representation
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
Daniel Karlsson, Petru Eles, Zebo Peng
ASM
2010
ASM
15 years 2 days ago
Automatic Verification for a Class of Proof Obligations with SMT-Solvers
Abstract. Software development in B and Event-B generates proof obligations that have to be discharged using theorem provers. The cost of such developments therefore depends direct...
David Déharbe
SEFM
2005
IEEE
15 years 3 months ago
From RT-LOTOS to Time Petri Nets New Foundations for a Verification Platform
The formal description technique RT-LOTOS has been selected as intermediate language to add formality to a real-time UML profile named TURTLE. For this sake, an RT-LOTOS verificat...
Tarek Sadani, Pierre de Saqui-Sannes, Jean-Pierre ...
79
Voted
WSC
1998
14 years 11 months ago
Validation and Verification of the Simulation Model of a Photolithography Process in Semiconductor Manufacturing
Simulation modeling provides an effective and powerful approach for capturing and analyzing complex manufacturing systems. More and more decisions are based on computer generated ...
Nirupama Nayani, Mansooreh Mollaghasemi
CDC
2010
IEEE
118views Control Systems» more  CDC 2010»
14 years 4 months ago
A state-based framework for supervisory control synthesis and verification
We extend an existing model-based framework for supervisory control synthesis with generalized control and verification state-based requirements. The former stem from the need for ...
Jasen Markovski, Dirk A. van Beek, Rolf J. M. Theu...