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» Efficient and User-Friendly Verification
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DAC
2005
ACM
14 years 11 months ago
Matlab as a development environment for FPGA design
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algo...
Tejas M. Bhatt, Dennis McCain
ATVA
2009
Springer
142views Hardware» more  ATVA 2009»
15 years 1 months ago
TAPAAL: Editor, Simulator and Verifier of Timed-Arc Petri Nets
TAPAAL is a new platform independent tool for modelling, simulation and verification of timed-arc Petri nets. TAPAAL provides a stand-alone editor and simulator, while the verifica...
Joakim Byg, Kenneth Yrke Jørgensen, Jir&iac...
CAV
2007
Springer
114views Hardware» more  CAV 2007»
15 years 1 months ago
Configurable Software Verification: Concretizing the Convergence of Model Checking and Program Analysis
In automatic software verification, we have observed a theoretical convergence of model checking and program analysis. In practice, however, model checkers are still mostly concern...
Dirk Beyer, Thomas A. Henzinger, Grégory Th...
ICDCSW
2000
IEEE
15 years 1 months ago
Compositional Verification of a Third Generation Mobile Communication Protocol
Model-checking has turned out to be an efficient and relatively easy-to-use technique in the verification of formally described programs. However, there is one major drawback in u...
Sari Leppänen, Matti Luukkainen
SPIN
2000
Springer
15 years 1 months ago
Logic Verification of ANSI-C Code with SPIN
We describe a tool, called AX, that can be used in combination with the model checker SPIN to efficiently verify logical properties of distributed software systems implemented in A...
Gerard J. Holzmann