7 search results - page 2 / 2 » Efficient and accurate gate sizing with piecewise convex del... |
DAC
2005
ACM
15 years 10 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
TCAD
2008
14 years 9 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...